1. Field of the Invention
The present invention relates to digital display units used in systems such as notebook computers, and more specifically to a method and apparatus for supporting spread spectrum clocking (SSC) in a digital display unit.
2. Related Art
Digital display units generally refer to devices containing a display panel which is formed of discrete points referred to as pixel elements. An image is generally displayed by appropriate activation to various degrees/colors, etc., of the individual pixel elements of a display panel as is well known in the relevant arts.
A digital display unit may be viewed as containing circuits (“controller circuit”) which receive various input signals from an external source (e.g., a display controller contained in a host), and generate control and data signals to cause images (represented by input signals) to be displayed on a display panel. The control signals generally control various panel related circuits.
One such control signal is which indicates the transition from one line to the next, and may be referred to as horizontal demarcation line or horizontal line demarker. The horizontal line demarkers may be used to generate other control signals which drive the display panel. The horizontal line demarkers may need to be generated in vertical blanking period (VBL) as well. As is well known, VBL refers to the time duration between two successive image frames contained in the input signals.
A prior digital display unit may receive a HSYNC signal which indicates the transition between horizontal lines even during the VBL. As is well known, HSYNC signals are generally generated associated with analog display signals designed for CRT monitors. The transitions in HSYNC signals may be used to generate the horizontal line demarcation signals in digital display units as is well known in the relevant arts.
However, an external source generating input signals (for the digital display unit) may not generate HSYNC signals (for example, because support for CRT monitors is no longer required). Accordingly, a digital display unit may need to generate line demarker signals in the absence of HSYNC signals.
A prior digital display unit may receive a data enable (DE) signal associated with pixel values, and generate line demarker signals according to the DE signal. As is well known, a DE signal is generally at a high logical level in the active data region/duration (in which pixel values are being received), and at a low logical level otherwise. The transitions on DE may thus be used as the basis for generating the line demarker signals.
Unfortunately, a DE signal continues to be low potentially throughout the entire VBL, and information on transitions of lines may not be directly available from examination of the DE signal. Particular challenges may be presented in spread spectrum clocking (SSC) type scenarios in which the number of pixels is not constant in the horizontal lines.
Therefore, what is needed is a method and apparatus for providing horizontal line demarcation signals for digital display panels in VBL in the absence of HSYNC signal in SSC type scenarios.